PNR: A Complete 28nm Physical Design Case Study Using Synopsys ICC2
DOI:
https://doi.org/10.63995/SOMI8527Keywords:
28nm Planar CMOS, Interconnect-Dominated Design, Physical Design, Place and Route, Routing Congestion, RTL-to-Signoff Flow, VLSI Physical ImplementationAbstract
The 28nm technology node remains an important component in present-day VLSI design because it provides a useful trade-off between power efficiency and fabrication cost. However, at this geometry, transforming a gate-level netlist into a signoff-compliant GDSII layout presents major physical design challenges that must be handled through optimization. A case study of the Physical Implementation (Place and Route) flow using the Synopsys IC Compiler II (ICC2) tool and a 28nm planar MOSFET technology is described. The paper explores methods to address high design density with a focus on power, performance, and area. With reduced feature size, routing congestion and interconnect delays become critical factors. Placement techniques such as congestion-aware placement, Concurrent Clock and Data optimization, and Multi-Corner Multi-Mode analysis are used to achieve timing closure. The work also investigates signal integrity, IR drop, layout-dependent effects, and provides a quantitative PPA analysis for reliable silicon signoff at 28nm.
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